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Description: jam CPU模拟器的设计与实现.其中包含设计文档-jam CPU Simulator Design and Implementation. which includes design documents
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Size: 104448 |
Author: 刘海洋 |
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Description: 32 risc cpu的参考设计,内涵完整的testbench-32 risc cpu s reference design, the connotation of complete Testbench
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Size: 2444288 |
Author: zys |
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Description:
一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
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Size: 275456 |
Author: wfs |
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Description: MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation.-MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD- one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source code is just a single page and easily understood. Both VHDL and Verilog versions are supplied. The package comes with assembler, emulator and extensive documentation.
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Size: 248832 |
Author: eldis |
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Description: IC内核的设计源码!其中包含MP3内核,CPU内核,I2C内核等多达式种IC设计的源码!-IC design of the kernel source code! MP3 contains one of the kernel, CPU core, I2C kernel up-type species such as IC design source!
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Size: 27160576 |
Author: hehuilong |
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Description: this file is cpu code in vhdl
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Size: 1024 |
Author: aydin |
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Description: this file is cpu code in vhdl
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Size: 3072 |
Author: aydin |
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Description: MIPS CPU设计实例的完整文档,台湾一个大学生的MIPS CPU完整设计文档,内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
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Size: 918528 |
Author: 李皓 |
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Description: NIOSII CPU设计实例,包括AVOLON总线特点和时序要求-NIOSII CPU design examples, including AVOLON bus characteristics and timing requirements
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Size: 138240 |
Author: 石林 |
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Description: RC4 Encrpytion
1.Encrpyt strings
2.Create pairs of keys for encoding and decoding automatically
3.Present the crptograph
4.Decode the crptograph to get the plaintext
-This CPU has basic instruction set, and we utilize its instruction set
to generate a program to verify its performance. Four parts constitute
a simple CPU: the control unit, the internal registers, the ALU and
instruction set.
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Size: 34816 |
Author: Jane |
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Description: 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
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Size: 774144 |
Author: 孟霑 |
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Description: 32位元浮点CPU,用VHDL语言以类似组合语言的方式写成-32 floating-point CPU(VHDL)
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Size: 2048 |
Author: 朋友 |
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Description: 16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
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Size: 2048 |
Author: 朋友 |
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Description: alu8bit.Usefull in design simple CPU(for beginner)
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Size: 2048 |
Author: vhp |
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Description: CPU编程,比较低层的硬件编程的 chm 资料文件--
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Size: 2714624 |
Author: 张希行 |
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Description: CPU代码-VHDL语言,实现了CPU的基本功能。-CPU code-VHDL language, the realization of the basic functions of the CPU.
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Size: 10240 |
Author: komavenn |
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Description: 8位CPU软核设计与应用研究-8-bit CPU design and application of soft-core research .......
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Size: 6958080 |
Author: steven |
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Description: 基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....
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Size: 64512 |
Author: steven |
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Description: DLX CPU VHDL CODE UNIVERSITY
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Size: 202752 |
Author: zahir Parkar |
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Description: 用Verilog 编写的8位risc cpu,行为级描述,可综合-6 bits risc cpu by Verilog
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Size: 132096 |
Author: 徐明 |
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